1 features ? f a st r e ad a c ce s s t i me - 7 0 ns ? lo w - p o w e r c m o s o p e r a t i o n C 100 m mm m a max. standby C 20 ma max. active at 5 mhz ? jedec standard packages ? 2 8-l e ad 6 0 0 - mil w in dow ed cd il ? 3 2-l e ad w in do we d l c c / j l cc C 2 8- l e ad cu s t om ? 5v 10% supply ? hi g h -rel i a bi l ity a tm el c m o s di e t e c hn o lo g y C 2,000v esd protection C 200 ma latchup immunity ? r a pi d ? a t me l p r og r a m mi n g a lg o r i thm - 1 0 0 m m m m s / b y te (typi c al) ? cmos and ttl compatible inputs and outputs ? integrated product identification code ? c o mm e r c ial , ind u stria l , mil t e mp e r ature ran g e s i n c hi - re l / d mb/8 883 5004/5005 description th e f t 27 c 512 r i s a l o w - po w e r , h i gh - p e r f o r ma n c e 524 , 28 8 - b it u v e r a s ab le p r o g r am - ma b l e r ea d o n l y m em o r y ( uv e p r o m ) o r g an i z e d 6 4 k b y 8 b i t s . it r e qu i r e s o n l y o n e 5 v power supply in normal read mode operation. any byte can be accessed in less than 45 ns, eliminating the need for speed reducing wait states on high-performance microprocessor systems. at m e l ? s d ie i n c m o s t e c h no l og y p r o v i de s h i gh - s pe e d, l o we r a c t i ve p o w e r c o n s u m p- t i on , a n d sig n ific a nt l y fas t e r p r o g r amm i ng . po w e r cons u mp t ion is typ i cally o n ly 8 m a in active mode and less than 10 m a in standby. 512k (64k x 8) u v ep r om f t 27 c 51 2 r 512k eprom pin configurations pin name function a0 to a15 addresses o0 - o7 outputs ce chip enable oe /vpp output enable/vpp nc no connect l cc / j lc c t o p v i e w n o t e : l c c / j lc c p a c k a g e p i n s 1 a n d 17 are dont connect. 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc o0 a8 a9 a11 nc oe/vpp a10 ce o7 o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 o1 o2 gnd nc o3 o4 o5 a7 a12 a15 nc vcc a14 a13 ( c onti n u ed) cd il t o p vi e w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o0 o1 o2 gnd vcc a14 a13 a8 a9 a11 oe/vpp a10 ce o7 o6 o5 o4 o3
f t 2 7 c 5 1 2 r 2 t h e f t 27 c 51 2 r i s a v a i l ab l e i n a c h o i c e of i nd u s t r y s t an- da r d jedec - app r o v ed u v er as a ble re - p r og r ammable c era mi c cd il , l cc, j l cc , cu st om pa c k a ge s . a l l de v i c e s fe a t u r e tw o - l i n e c ont r o l ( c e , oe ) to give designers the flexibility to prevent bus contention. wi t h 6 4 k b y t e st o r ag e ca p abi l i ty , t h e f t 2 7 c 5 12 r a llo w s firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. fo rce 's 2 7 c512r h a s addi t i ona l feat u r e s to en s u r e hi g h q ua l ity an d e f f i cie n t p r od u ct i on use . t h e r ap i d ? p r og r a m- ming algorithm reduces the time required to program the part and guarantees reliable programming. programming time is typically only 100 m s/byte. the integrated product identification code electronically identifies the device and manufacturer. this feature is used by industry standard programming equipment to select the proper programming a l go r i t hm s a n d v o l t ag e s. a t me l die gi ve s at mel s i gna tu re . system considerations switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. unless accommodated by the system design, these tran- sients may exceed data sheet limits, resulting in device non-conformance. at a minimum, a 0.1 m f high frequency, low inherent inductance, ceramic capacitor should be uti- lized for each device. this capacitor should be connected between the v cc and ground terminals of the device, as close to the device as possible. additionally, to stabilize the supply voltage level on printed circuit boards with large eprom arrays, a 4.7 m f bulk electrolytic capacitor should be utilized, again connected between the v cc and ground terminals. this capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
f t27 c 51 2 r 3 block diagram notes: 1. x can be v il or v ih . 2. refer to programming characteristics. 3. v h = 12.0 0.5v. 4. two identifier bytes may be selected. all ai inputs are held low (v il ), except a9 which is set to v h and a0 which is toggled low (v il ) to select the manufacturers identification byte and high (v ih ) to select the device code byte. absolute maximum ratings* temperature under bias............................... -55c to + 125c *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions beyond those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc which may undershoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc which may overshoot to +7.0 volts for pulses of less than 20 ns. storage temperature .................................... -65c to + 150c voltage on any pin with respect to ground ........................................-2.0v to + 7.0v (1) voltage on a9 with respect to ground .....................................-2.0v to + 14.0v (1) v pp supply voltage with respect to ground ......................................-2.0v to + 14.0v (1) operating modes mode\pin ce oe /v pp ai outputs read v il v il ai d out output disable v il v ih x (1) high z standby v ih x (1) x high z rapid program (2) v il v pp ai d in pgm inhibit v ih v pp x (1) high z product identification (4) v il v il a9 =v h (3) a0 = v ih or v il a1 - a15 = v il identification code
f t 2 7 c 5 1 2 r 4 notes: 1. v cc must be applied simultaneously with or before oe /v pp , and removed simultaneously with or after oe /v pp .. notes: 2, 3, 4, 5. - see ac waveforms for read operation. dc and ac operating conditions for read operation f t 27 c 5 12r -4 5 - 5 5 - 7 0 - 9 0 -1 2 - 15 operating te m p . ( c a s e ) co m . 0 c - 7 0 c 0c - 70 c 0 c - 7 0 c 0 c - 7 0 c i n d . - 4 0c - 85 c - 4 0 c - 8 5 c -4 0 c - 8 5 c -40c - 85c mi l -55oc-125oc -55oc-125oc -55oc-125oc -55oc-125oc v cc supply 5v 10% 5v 10% 5v 10% 5v 10% 5v 10% 5v 10% dc and operating characteristics for read operation symbol parameter condition min max units i li input load current v in = 0v to v cc com., ind, 1 m a mi l . 5 m a i lo output leakage current v out = 0v to v cc com., ind, 5 m a mi l . 1 0 m a i sb v cc (1) standby current i sb1 (cmos), ce = v cc 0.3v 100 m a i sb2 (ttl), ce = 2.0 to v cc + 0.5v 1 ma i c c v cc act i v e cur r en t f = 5 mh z , i o u t = 0 m a , ce / in d , mi l = v i l 2 0 / 2 5 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 m a2.4v ac characteristics for read operation symbol parameter condition f t 2 7 c 5 1 2 r units -45 -55 -70 -90 -12 -15 min max min max min max min max min max min max t acc (3) address to output delay ce = oe /v pp = v i l 7 0 9 0 12 0 1 5 0 n s t ce (2) ce to output delay oe /v pp = v i l 7 0 9 0 12 0 1 5 0 n s t oe (2)(3) oe /v pp to output delay ce = v i l 3 0 3 5 3 5 4 0 ns t df (4)(5) oe /v pp or ce high to output float, whichever o c c u rre d fir s t 2 5 2 5 3 0 3 5 ns t oh output hold from address, ce or oe /v pp , wh i c h e v e r o c c u rred fir s t 0 0 0 0
f t27 c 51 2 r 5 ac waveforms for read operation (1) notes: 1. timing measurement reference level is 1.5v for -45 and -55 devices. input ac drive levels are v il = 0.0v and v ih = 3.0v. timing measurement reference levels for all other speed grades are v ol = 0.8v and v oh = 2.0v. input ac drive levels are v il = 0.45v and v ih = 2.4v. 2. oe /v pp may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce . 3. oe /v pp may be delayed up to t acc - t oe after the address is valid without impact on t acc . 4. this parameter is only sampled and is not 100% tested. 5. output float is defined as the point when data is no longer driven. input test waveforms and measurement levels output test load note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. t r , t f < 5 ns (10% to 90%) for -45 and -55 devices only: t r , t f < 20 ns (10% to 90%) for -70, -90, -12, -15, and -20 devices: note: c l = 100 pf including jig capacitance, except for the -45 and -55 devices, where c l =30 pf. pin capacitance (f = 1 mhz t = 25c) (1) typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
f t 2 7 c 5 1 2 r 6 programming waveforms (1) notes: 1. the input timing reference is 0.8v for v il and 2.0v for v ih . 2. t oe and t dfp are characteristics of the device but must be accommodated by the programmer. dc programming characteristics t a = 25 5c, v cc = 6.5 0.25v, oe /v pp = 13.0 0.25v symbol parameter test conditions limits units min max i li input load current v in = v il ,v ih 10 m a v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 m a2.4 v i cc2 v cc supply current (program and verify) 25 ma i pp2 oe /v pp current ce = v il 25 ma v id a9 product identification voltage 11.5 12.5 v
f t27 c 51 2 r 7 notes: 1. v cc must be applied simultaneously or before oe /v pp and removed simultaneously or after oe /v pp . 2. this parameter is only sampled and is not 100% tested. output float is defined as the point where data is no longer driven see timing diagram. 3. program pulse width tolerance is 100 m sec 5%. ac programming characteristics t a = 25 5c, v cc = 6.5 0.25v, oe /v pp = 13.0 0.25v symbol parameter test conditions (1) limits units min max t as address setup time input rise and fall times (10% to 90%) 20ns input pulse levels 0.45v to 2.4v input timing reference level 0.8v to 2.0v output timing reference level 0.8v to 2.0v 2 m s t oes oe /v pp setup time 2 m s t oeh oe /v pp hold time 2 m s t ds data setup time 2 m s t ah address hold time 0 m s t dh data hold time 2 m s t dfp ce high to output float delay (2) 0 130 ns t vcs v cc setup time 2 m s t pw ce program pulse width (3) 95 105 m s t dv data valid from ce (2) 1 m s t vr oe /v pp recovery time 2 m s t prt oe /v pp pulse rise time during programming 50 ns ft 27c512r int e g r ated p r oduct identifi c a tion c ode-atmel die codes pins hex data a0 o7 o6 o5 o4 o3 o2 o1 o0 manufacturer 000011110 1e device type 100001101 0d
f t 2 7 c 5 1 2 r 8 rapid programming algorithm a 100 m s ce pulse width is used to program. the address is set to the first location. v cc is raised to 6.5v and oe /v pp is raised to 13.0v. each address is first programmed with one 100 m s ce pulse without verification. then a verifica- tion/reprogramming loop is executed for each address. in the event a byte fails to pass verification, up to 10 succes- sive 100 m s pulses are applied with a verification after each pulse. if the byte fails to verify after 10 pulses have been applied, the part is considered failed. after the byte verifies properly, the next address is selected until all have been checked. oe /v pp is then lowered to v il and v cc to 5.0v. all bytes are read again and compared with the original data to determine if the device passes or fails.
f t27 c 51 2 r 9 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 7 0 2 0 0 . 1 ft 2 7 c 5 1 2 r - xx d c f t 2 7 c 5 1 2 r - xx l c f t 2 7 c 5 1 2 r - xx k c f t 2 7 c 5 1 2 r - xx - xxx w in cd il w in lcc w in j l cc xx x - cu st om commercial (0 c to 70 c) 2 0 0 . 1 f t 2 7 c 5 1 2 r - xx d i f t 2 7 c 5 1 2 r - xx li f t 2 7 c 5 1 2 r - xx ki f t 2 7 c 5 1 2 r - xx ti - x xx wincdil winlcc winjlcc xxx-custom industrial (-40 c to 85 c) 2 0 0 . 1 f t 2 7 c 5 1 2 r - xx dm f t 2 7 c 5 1 2 r - xx lm f t 2 7 c 5 1 2 r - xx km wincdil winlcc winjlcc mi li tar y (- 55 c to 1 2 5 c) package type j l cc 3 2 - l ea d , cer am ic j - l ea d ed wi nd owe d c h i p car r i e r ( j lcc) cd il 2 8 - l ea d , 0 . 60 0 " w i d e , c era mi c wi nd owe d d ua l in l i n e p a c k a g e (p d ip) l cc 32 - l ea d , ce ra mi c wi nd ow ed l cc (l cc ) d mb / d m b 8 dm b = te s te d to m il - st d - 88 3 me th od 5 00 4 d m b 8 = te ste d to mi l- st d - 88 3 me th od 500 5
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